In a standard semiconductor memory device, data read is performed by detecting and amplifying a signal present in a bit line at a certain timing in a sense amplifier circuit. The signal depends on data stored in a memory cell. To increase operational speed of the semiconductor memory device, it is required that a time from rise of a select signal of the memory cell to sense amplifier activation be shortened.
However, if the sense amplifier circuit is activated too early, there is an increased possibility that a detecting/amplifying operation of the sense amplifier circuit is started before a sufficient potential difference appears in a bit line pair connected to a selected memory cell, thus causing a possibility of a false read to become higher. It is therefore required to set an optimum timing at which a false read does not occur and operational speed can be increased. Activation timing of the sense amplifier circuit depends on dimension (size, width, etc.) of the memory cell array. Above all, a memory macro generator need to handle various types of memory configurations, without changing a circuit configuration thereof. Hence, it needs to set an optimum timing according to the dimension of the memory cell array.
Under such circumstances, as a technique for generating an activation signal of the sense amplifier with an appropriate timing, the following semiconductor memory device is known. In this semiconductor device, a signal read from a dummy cell is delayed by a delay circuit, and this delayed signal is supplied to the sense amplifier as a sense amplifier activation signal. This device includes dummy cells configured to store certain data in a fixed manner and having a structure identical or similar to those of a memory cell array. Moreover, a select signal is inputted to a dummy word line connected to one of these dummy cells, and, as a result, a signal read from the dummy cell to a bit line pair is delayed for a certain time by the delay circuit to generate the sense amplifier activation signal, and this sense amplifier activation signal is inputted to the sense amplifier. By forming a dummy word line and a dummy bit line having a dimension compatible with that of the memory cell array, an optimum sense amplifier activation signal compatible with memory cell dimension may be generated.
However, there is a problem that the above-described dummy cells, dummy word lines, and dummy bit lines occupy a large circuit area in the memory device, thereby hindering miniaturization of the memory device. In addition, since there is a need to fix the data stored in a dummy cell at either of “1” or “0”, the dummy cell must have a different layout to that of a memory cell MC. As a result, the dummy cell array having the dummy cells arranged therein has a different continuity to the memory cell array having the memory cells arranged therein and requires design of a separate cell structure.